We have published an application note on to how to best utilize the fully automatic and fail-safe bias circuit feature in our line of high power GaN transistors that only requires a single positive voltage power supply.
As GaN HEMT transistors are depletion mode devices - requiring a negative voltage for the gate and a positive voltage for the drain - this dual voltage requirement can raise havoc when reducing biasing circuitry is an objective. Additionally, since they are depletion mode devices, it is critically important to supply the negative voltage to the gate before any positive voltage is applied to the drain, as the transistor will inherently draw its maximum possible drain current from the supply. This leads to excessive thermal dissipation and device burnout. For these reasons, Integra developed a fully automatic and fail-safe bias circuit for its GaN transistors that only requires a single positive voltage power supply.
Our Application Note 004 "Automatic & Fail-Safe Biasing of GaN Transistors" describes how a diode detector connected to a coupler is used to sense when an RF signal is applied to the transistor. There are two stages of operation of this circuit. In the initial phase, is where a negative voltage is applied to the gate of the GaN transistor such that when the drain bias is subsequently applied then the device will be biased at pinch-off i.e. no drain current will flow save for the finite leakage current of the transistor as specified in the transistor's data sheet. This bias sequence of first applying a negative gate voltage followed by the application of the positive drain bias is fail-safe and fully automatic, and is controlled by the circuit. We refer to this circuit as a Gate Pulsing and Sequencing circuit (GPS), and this first phase of operation is the sequencing aspect.
There are many important points to note about using this GPS circuit. One is that there is a finite delay between the application of an RF pulse at the input and the GaN device turning on, and likewise for the turn off sequence, and these delays and the associated rise and fall times are detailed in the application note. Another point is that this circuit has a very beneficial effect on reducing the amount of shot noise injected into the receiver during the RF-off period. Additional details portrayed in the application note include a presentation of time delay and rise/fall time measurements showing the circuit suppressing the output noise in the RF-off period by >30 dB for a 500 W GaN transistor biased with a quiescent current of 200 mA.
High power amplifier designers will learn the advantages and operations of these circuits, and temperature compensation details required for effective utilization of these innovative GaN transistors.
Download the application note "Automatic & Fail-Safe Biasing of GaN Transistors" and contact our technical support team with any questions regarding your GaN transistors.